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P. Schiffmann, An ARM Porting Story - Optimizing a RBF Interpolation Solver for Energy on Heterogeneous Systems. GoingARM Workshop, ISC, Frankfurt, Germany, 2017.
F. Mantovani, Butterfly effect of porting scientific applications to ARM-based platforms. GoingARM Workshop, ISC, Frankfurt, Germany, 2017.
M. Benito, Vallejo, E., Beivide, R., and Izu, C., Extending commodity OpenFlow switches for large-scale HPC deployments. 2017 IEEE 3rd International Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era (HiPINEB), Austin, Texas, USA, 2017.
R. Rusitoru and Beard, J., GoingARM workshop. ISC, Frankurt, Germany, 2017.
R. Nishtala, Carpenter, P., Petrucci, V., and Martorell, X., Hipster: Hybrid Task Manager for Latency-Critical Cloud Workloads. The 23rd IEEE Symposium on High Performance Computer Architecture, 2017.
M. Popov, Akel, C., Chatelain, Y., Jalby, W., and Castro, Pde Oliveir, Piecewise holistic autotuning of parallel programs with CERE, 2017.
F. Mantovani, Power monitoring on ARM-based HPC clusters: experiences from young and old. EECS Seminar 2017 Energy Efficient Computing Systems, NTNU Norway, 2017.
C. Camarero, Martínez, C., and Beivide, R., Random Folded Clos Topologies for Datacenter Networks. 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), Austin, Texas, USA, 2017.
I. Pérez, Castillo, E., Beivide, R., Vallejo, E., Bosque, J. Luis, Moreto, M., Casas, M., and Valero, M., Analyzing the Impact of Parallel Programming Models in NoCs of Forthcoming CMP Architectures. Proceedings of the EMerging Technology (EMiT) Conference, Barcelona, Spain, 2016.
S. McIntosh-Smith, Hunt, R., Price, J., and Vesztrocy, A., Application-Based Fault Tolerance Techniques for Sparse Matrix Solvers. International Journal of High Performance Computing Applications, 2016.
L. Fialho, ARM on HPC: status of commonly used performance analysis tools, Cambridge, United Kingdom, 2016.
J. Gracia and Zhou, H., Asynchronous progress design for a MPI-based PGAS one-sided communication system. 22nd IEEE International Conference on Parallel and Distributed Systems (ICPADS 2016), Wuhan, China, 2016.
E. Castillo, Moreto, M., Casas, M., Alvarez, L., Vallejoz, E., Chronaki, K., Badia, R., Bosquez, J. Luis, Beividez, R., Ayguadé, E., Labarta, J., and Valero, M., CATA: Criticality Aware Task Acceleration for Multicore Processors. International Parallel and Distributed Parallel Symposium (IPDPS) 2016, Chicago, USA, 2016.
O. Subasi, Unsal, O., Labarta, J., Yalcin, G., and Cristal, A., Crc-based memory reliability for task-parallel hpc applications, IPDPS’2016, 2016.
J. Wanza Weloli, Bilavarn, S., Derradji, S., Belleudy, C., and Lesmanne, S., Efficiency Modeling and Analysis of 64-bit ARM Clusters for HPC. 2016 Euromicro Conference on Digital System Design (DSD) , 2016.
M. Nachtmann and Gracia, J., Enabling Model-Centric Debugging for Task-Based Programming Models -- a Tasking Control Interface, Springer, 2016, p. 147--160.
B. Pérez, Stafford, E., Bosque, J. Luis, and Beivide, R., Energy Efficiency Evaluation in Heterogeneous Computers. Barcelona, Spain, Proceedings of the EMerging Technology (EMiT) Conference, 2016.
B. Pérez, Stafford, E., Bosque, J. Luis, and Beivide, R., Energy efficiency of load balancing for data-parallel applications in heterogeneous systems. Proceedings of the 16th International Conference on Computational and Mathematical Methods in Science and Engineering, Cádiz, Spain, 2016.
S. McIntosh-Smith, Fault Tolerant Sparse Iterative Solvers, SIAM PP16 in Resilience Toward Exascale Computing track, 2016.
A. Butko, BRUGUIER, F., Gamatié, A., Sassatelli, G., NOVO, D., Torres, L., and Robert, M., Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy Exploration, 21-23 september 2016. IEEE MCSoC : International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016.
V. Marjanovic, Gracia, J., and Glass, C. W., HPC Benchmarking: Problem Size Matters. Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems (PMBS16), SC16 Salt Lake City, USA, 2016.
N. Rajovic, Rico, A., Mantovani, F., Ruiz, D., Vilarrubi, J. Oriol, Gomez, C., Backes, L., Nieto, D., Servat, H., Martorell, X., Labarta, J., Ayguadé, E., Adeniyi-Jones, C., Derradji, S., Gloaguen, H., Lanucara, P., Sanna, N., Mehaut, J. - F., Pouget, K., Videau, B., Boyer, E., Allalen, M., Auweter, A., TAFANI, D., Brayford, D., Brömmel, D., Halver, R., Meinke, J. H., Beivide, R., Benito, M., Vallejo, E., Valero, M., and Ramirez, A., The Mont-Blanc prototype: An Alternative Approach for HPC Systems, 2016.
T. Grass, Allande, C., Armejach, A., Rico, A., Ayguadé, E., Labarta, J., Valero, M., Casas, M., and Moreto, M., MUSA: A Multi-Level Simulation Infrastructure for Next-Generation HPC Machines. SC16, Salt Lake City, USA, 2016.
M. Popov, Akel, C., Jalby, W., and Castro, Pde Oliveir, Piecewise Holistic Autotuning of Compiler and Runtime Parameters. Euro-Par 2016, 22nd International European Conference on Parallel and Distributed Computing, Grenoble, France, 2016.