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Arm SVE Hackathon: “Arm Scalable Performance for HPC and ML”

February 21, 2019

Our partners Arm and BSC are organising a hackathon that will rely on Mont-Blanc 3’s Dibona prototype. Don’t miss this opportunity to test our prototype and investigate the impact of novel SVE extensions on HPC and Machine Learning applications.

This hackathon targets application developers that are interested in investigating the impact of novel SVE extensions on High Performance Computing (HPC) and Machine Learning (ML) applications. Arm researchers and engineers will introduce the different HPC tools available from Arm including compilers, math libraries, debugging and profiling tools. The hackathon will focus on the benefits of SVE extensions in the context of HPC and ML kernels and applications. The instructors will guide attendees to vectorize codes through compilation, refactoring and intrinsics. The vectorization examples will showcase the features of SVE that help provide higher performance and energy efficiency by increasing utilization of vectors, improving data movement and exploiting in-core acceleration of important compute patterns. To ease this experience, the organizers will provide access to HPC machines with all the required tools already installed.

This is the second edition of the Arm SVE Hackathon series. The first one was held at SC18 (find more information here: