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BSC Installs New ARM-Based Prototype

November 6, 2012

BARCELONA, Spain, Nov. 6 – With energy efficiency as an objective in HPC, the Barcelona Supercomputing Center (BSC) has deployed a new prototype cluster to explore alternate architectures. The prototype combines energy-efficient ARM cores with a mobile GPU accelerator, and currently achieves 5 GFLOPS per Watt in Single Precision computation (0.8 GFLOPS/Watt in Double Precision), improving on current accelerator-based systems for GPU-centric applications.

Co-funded by the Partnership for Advanced Computing in Europe (PRACE) initiative, the cluster, built of 16 nodes of Quad-core Tegra3 SoC plus a Quadro 1000M mobile GPU connected through a Gigabit Ethernet network, is based on the previous experience of the 256-node Tegra2 cluster deployed in 2011.

PRACE is exploring a set of prototypes to test and evaluate promising new technologies for future multi-PFLOPS systems. In this context some pre-production prototypes have already been installed at HPC centres of PRACE partners such as France (GENCI), Sweden (SNIC) and Ireland (ICHEC), among others. A common goal of all prototypes is to evaluate energy efficiency to estimate the suitability of those components for future high-end systems.

“Our goal is to build and evaluate potentially interesting architectures, even before they are mature enough for commercial exploitation, so that they can be well understood and ready to use when they reach the market.”, says Alex Ramirez, Heterogeneous Architectures Group Leader at the BSC.

The new Spanish prototype will be located on the BSC premises. It will be used to develop the system software stack on this new kind of architectures, perform scalability tests on a moderate number of computer nodes, and evaluate how BSC’s OmpSs programming model mitigates the impact of limited memory and bandwidth from using low-end components. These prototypes accelerate the software development, and help computer architects investigate different hardware possibilities and programming paradigms towards the future design of energy efficient supercomputers.

Technical details of a single node

NVIDIA CARMA developer board manufactured by SECO
CPU: NVIDIA Tegra 3 quad-core ARM Cortex-A9
GPU: NVIDIA Quadro 1000M (96 CUDA cores)
Memory: 2GB (CPU) + 2GB (GPU)
270 single precision GFLOPS

Birds-of-Feather session at SC12

In order to know more about these technologies, PRACE organizes a special Birds-of-Feather session “PRACE Future Technologies Evaluation Results” on Wednesday, 14th November during the SC12 conference ( in Salt Lake City (USA). A synopsis of the assessments and selected results of these innovative technologies will be presented in a short series of presentations and discussions. More information on

More information:

About Barcelona Supercomputing Center

Centro Nacional de Supercomputación (BSC) hosts the supercomputer MareNostrum. It also has well-known supercomputing research groups that develop tools for academia and industry. BSC focuses its research areas in Computer Sciences, Life and Earth Sciences and Computer Applications in Science and Engineering. In the context of this multi-disciplinary approach, BSC has more than 350 researchers and experts in HPC (High Performing Computing) and 100 of those are from outside Spain. BSC was constituted as a public consortium formed by the current Spanish Ministry of Economy and Competitivity (Ministerio de Economía y Competitividad), the Department of Economy and Knowledge of the Catalan Government and the Technical University of Catalonia. Barcelona Tech (UPC), and is headed by Professor Mateo Valero. In 2011, the BSC-CNS was recognized as a “Severo Ochoa Centre of Excellence” for its contributions and research agenda in the area of computing and applications. In the first edition of the Severo Ochoa programme, the Ministry of Science and Innovation selected 8 research centres and units in Spain to be among the best in the world in their respective fields.


The Partnership for Advanced Computing in Europe (PRACE) is an international non-profit association with its seat in Brussels. The PRACE Research Infrastructure (RI) provides a persistent world-class High Performance Computing (HPC) service for scientists and researchers from academia and industry. The Implementation Phase of PRACE receives funding from the EU’s Seventh Framework Programme (FP7/2007-2013) under grant agreements n° RI-261557 and n° RI-283493.