Skip to content

Exascale supercomputing on a million mobile phones

June 3, 2013

There has been a great deal of recent interest about building servers on ARM processors, and there are indeed a good number of reasons to build HPC on ARM processors as well.

The most frequently quoted reason for using ARM is their superior energy efficiency. However, this is a highly controversial topic, and it has been argued that given current implementations, there is no fundamental reason for a RISC ISA (ARM) to be more energy efficient than a CISC ISA (x86).

However, there are more reasons for using ARM processors. A major one is the different business model on which ARM is built: separating the processor IP from the hardened SoC. This model allows for multiple providers, more competition, lower cost, faster improvements, better features, and shorter time to market. All of them desirable from the customer side.

The question is: who is going to survive among the many ARM-server providers that are emerging … if any. The entire server market is hardly large enough to sustain the current providers (Intel, AMD, IBM, Oracle), with Intel being the largest, shipping ~8M boxes in 2012.

There were over 750M smartphones sold in 2012, most of them with an ARM SoC in it. There seems to be more than enough room for multiple profitable providers (Apple, Samsung, Qualcomm, NVIDIA, Freescale, etc.)

It may very well happen that those mobile vendors decide to implement the minimal set of features required to make their SoC usable for servers … and take over the entire market with a cheaper product, that evolves faster, and has added features (such as an integrated GPU).

Such is the approach taken by the Mont-Blanc project: can we build HPC on a SoC initially targeted at the mobile market? Which are the missing features they should implement? What are the software challenges?

Mont-Blanc is one of the three projects funded by the European Commission under FP7 to develop the next generation of supercomputer hardware and software, with a clear goal of achieving Exascale performance by 2018-2020. If you want to learn more about Mont-Blanc, or the other EU Exascale projects, join us at the Birds-of-Feather session titled “Exascale Research – The European Approach” on Tuesday 18th June from 9-10am.

Biography of Alex Ramirez

Alex Ramirez is an associated professor in the Computer Architecture Department at the Universitat Politecnica de Catalunya, and leader of the Heterogeneous Architectures group at BSC. He has a BSc (’95), MSc (’97) and PhD (’02, awarded the UPC extraordinary award to the best PhD in computer science) in Computer Science from the Universitat Politecnica de Catalunya (UPC), Barcelona, Spain. He has been a summer student intern with Compaq’s WRL in Palo Alto, California for two consecutive years (’99-’00), and Intel’s Microprocessor Research Laboratory in Santa Clara (’01), and a visiting researcher at NXP (’07). He has co-authored over 100 papers in international conferences and journals, supervised 9 PhD students, and participated as principal investigator in the SARC, ACOTES, ENCORE and HiPEAC European Projects. He currently leads the Mont-Blanc FP7 project. In 2010 he was awarded the first Agustin de Betancourt award of the Spanish Royal Academy of Engineering to a young researcher.