New ARM interconnect technology paves the way for scalable system-on-chip (SoC) solutions for network infrastructure and servers
CAMBRIDGE, UK and LINLEY TECH PROCESSOR CONFERENCE, SAN JOSE – October 10, 2012 – To address the significant increase in data over the next 10-15 years, and the demand for more energy-efficient network infrastructure and servers, ARM has announced the ARM® CoreLink™ CCN-504 cache coherent network. This advanced system intellectual property (IP) can deliver up to one terabit of usable system bandwidth per second. It will enable SoC designers to provide high-performance, cache coherent interconnect for ‘many-core’ enterprise solutions built using the ARM Cortex™-A15 MPCore™ processor and next-generation 64-bit processors.
LSI, a leading designer of intelligent semiconductors that accelerate storage, mobile networking and client computing, and Calxeda, an innovative supplier of disruptive SoC technology for the server market, are lead licensees for the CoreLink CCN-504 launch.
ARM has also unveiled the new ARM CoreLink DMC-520 dynamic memory controller that has been designed and optimized to work with the CoreLink CCN-504. The new dynamic memory controller provides a high-bandwidth interface to shared off-chip memory, such as DDR3, DDR3L and DDR4 DRAM. It is part of an integrated ARM DDR4 interface solution incorporating ARM Artisan® DDR4/3 PHY IP planned for introduction in 2013.
“Calxeda and ARM have been working closely to meet the demands of the datacenter since ARM’s initial investment in our company in 2008, and we are beginning to see the fruits that relationship,” said Barry Evans, co-founder and CEO, Calxeda. “We are already building our next generation datacenter-class solutions using this new ARM CoreLink technology, and think we will once again send shockwaves across the industry when they are announced.”
“To meet the demands of rapidly growing mobile network traffic, LSI and ARM have worked closely to drive a feature-rich on-chip interconnect that can serve as the backbone for industry-leading many-core system-on-chip devices,” said Gene Scuteri, vice president of engineering, LSI. “ARM expertise in processor and interconnect technology, guided by LSI’s deep understanding of networking and compute workloads, has delivered a robust, carrier-grade interconnect that will deliver scalable, deterministic performance and quality of service for today’s most advanced networks.”
CoreLink CCN-504 is the first in a family of products. It enables a fully-coherent, high-performance many-core solution that supports up to 16 cores on the same silicon die. The CoreLink CCN-504 enables system coherency in heterogeneous multicore and multi-cluster CPU/GPU systems by enabling each processor in the system to access the other processor caches. This reduces the need to access off-chip memory, saving time and energy, which is a key enabler in systems based on ARM big.LITTLE™ processing, a new paradigm that can deliver both high-performance, required for content creation and consumption, and extreme power efficiency for extended battery life.
“As the amount of data used increases exponentially over the next 10-15 years, the CoreLink CCN-504 and DMC-520 will play an important role by providing high-performance system IP solutions for many-core applications,” said Tom Cronk, deputy general manager, processor division, ARM. “This ensures quality of service and coherent operation across the system, and enables SoC designers to efficiently prioritize and handle wide data flows with optimum latency.”
The CoreLink CCN-504 supports both the current-generation high-end Cortex-A15 processor and future ARMv8 processors and is the first in a family of network-based interconnect products planned by ARM. Building on the success of the AMBA® 4 ACE™ specification the CoreLink CCN-504 also benefits from ARM experience in hardware-based coherency, which enables improved energy-efficiency and lower latency than software coherency. Over 8000 AMBA 4 ACE specifications have been downloaded to date.
The CoreLink CCN-504 cache coherent network includes integrated level 3 (L3) cache and snoop filter functions. The L3 cache, which is configurable up to 16MB, extends on-chip caching for demanding workloads and offers low latency on-chip memory for allocation and sharing of data between processors, high-speed IO interfaces and accelerators. The snoop filter removes the need for broadcast coherency messaging, further reducing latency and power.
Availability: the ARM CoreLink CCN-504 cache coherent network is available to lead licensees now, and sampling in partner products in 2013.