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Stencil Codes on a Vector Length Agnostic Architecture

Armejach, A. - Caminal, H. - Cebrian, J. - González-Alberquilla, R. - Adeniyi-Jones, C. - Valero, M. - Casas, M. - Moreto, M.

Conference Paper

2018

Reducing Data Movement on Large Shared Memory Systems by Exploiting Computation Dependencies

Sanchez-Barrera, I. - Moreto, M. - Ayguadé, E. - Labarta, J. - Valero, M. - Casas, M.

Conference Proceedings

2018

Runtime-Guided Management of Stacked DRAM Memories in Task Parallel Programs

Alvarez, L. - Casas, M. - Labarta, J. - Ayguadé, E. - Valero, M. - Moreto, M.

Conference Proceedings

2018

TaskGenX: A Hardware-Software Proposal for Accelerating Task Parallelism

Chronaki, K. - Casas, M. - Moreto, M. - Bosch, J. - Badia, R.

Conference Paper

2018

Reducing Cache Coherence Traffic with a NUMA-Aware Runtime Approach

Caheny, P. - Alvarez, L. - Derradji, S. - Valero, M. - Moreto, M. - Casas, M.

Journal Article

2018

Task scheduling techniques for asymmetric multi-core systems

Chronaki, K. - Rico, A. - Casas, M. - Moreto, M. - Badia, R. - Ayguadé, E. - Labarta, J. - Valero, M.

Journal Article

2017

Analyzing the Impact of Parallel Programming Models in NoCs of Forthcoming CMP Architectures

Pérez, I. - Castillo, E. - Beivide, R. - Vallejo, E. - Bosque, J. - Moreto, M. - Casas, M. - Valero, M.

International Conferences

2016

CATA: Criticality Aware Task Acceleration for Multicore Processors

Castillo, E. - Moreto, M. - Casas, M. - Alvarez, L. - Vallejo, E. - Chronaki, K. - Badia, R. - Bosque, J. - Beivide, R. - Ayguadé, E. - Labarta, J. - Valero, M.

International Conferences

2016

European modular and power-efficient HPC processor
This project has received funding from the European Union's Horizon 2020 research and innovation program under grant agreement 779877
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