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Runtime-assisted cache coherence deactivation in task parallel programs

Caheny, P. - Alvarez, L. - Valero, M. - Moreto, M. - Casas, M.

Conference Paper

2018

Stencil Codes on a Vector Length Agnostic Architecture

Armejach, A. - Caminal, H. - Cebrian, J. - González-Alberquilla, R. - Adeniyi-Jones, C. - Valero, M. - Casas, M. - Moreto, M.

Conference Paper

2018

Reducing Data Movement on Large Shared Memory Systems by Exploiting Computation Dependencies

Sanchez-Barrera, I. - Moreto, M. - Ayguadé, E. - Labarta, J. - Valero, M. - Casas, M.

Conference Proceedings

2018

Runtime-Guided Management of Stacked DRAM Memories in Task Parallel Programs

Alvarez, L. - Casas, M. - Labarta, J. - Ayguadé, E. - Valero, M. - Moreto, M.

Conference Proceedings

2018

A scalable synthetic traffic model of Graph500 for computer networks analysis

Fuentes, P. - Benito, M. - Vallejo, E. - Bosque, J. - Beivide, R. - Anghel, A. - Rodríguez, G. - Gusat, M. - Minkenberg, C. - Valero, M.

Journal Article

2017

Reducing Cache Coherence Traffic with a NUMA-Aware Runtime Approach

Caheny, P. - Alvarez, L. - Derradji, S. - Valero, M. - Moreto, M. - Casas, M.

Journal Article

2018

FlexVC: Flexible Virtual Channel Management in Low-Diameter Networks

Fuentes, P. - Vallejo, E. - Beivide, R. - Minkenberg, C. - Valero, M.

Conference Paper

2017

Task scheduling techniques for asymmetric multi-core systems

Chronaki, K. - Rico, A. - Casas, M. - Moreto, M. - Badia, R. - Ayguadé, E. - Labarta, J. - Valero, M.

Journal Article

2017

European Approach Towards Energy Efficient High Performance Computing
This project has received funding from the European Union's Horizon 2020 research and innovation program under grant agreements n° 671697 and 779877
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