Mont-Blanc 2020 demonstrator
The Mont-Blanc 2020 demonstrator is a key output of the project.
The prototype will run on an emulator platform; it will be based on trace-based SVE traffic generators combined with the RTL model of the NoC and the full memory hierarchy. Its objectives:
- validation of the design and the associated toolchain in the context of real-life applications,
- cycle-accurate evaluation of performance at SoC level that will be extrapolated to predict the impact of MB2020 designs for a full HPC system targeting Exascale computing.
The Mentor Veloce emulation platform
Emulation is the process of using a hardware / software based platform that mimics the physical behaviour of an Integrated Circuit / System-on-Chip design. It is an essential process for the development of complex digital circuits. Mont-Blanc 2020 benefits from the Mentor Veloce2 emulator platform installed at its partner CEA.
One thousand times faster than traditional simulation tools, Veloce allows to test, debug and validate SoCs at an early stage of their design, using real-world data.
Mont-Blanc 3 prototype: Dibona
As part of the Phase 3 of Mont-Blanc, Atos built a new Arm-based prototype, which is available to the Mont-Blanc partners and end-users to test our software and scientific applications on a state-of-the-art Arm architecture.
It is named Dibona, after the Dibona peak in the French Alps, and it started operation in Fall 2017. It is based on 64 bit ThunderX2 processors from Marvell®, relying on the Arm® v8 instruction set. The prototype leverages the BullSequana X1000 infrastructure, including ultra efficient Direct Liquid Cooling – cooling with warm water. The full configuration includes:
- 48 bi-socket computes nodes
- ie. 96 Marvell® ThunderX2 CPUs (32 cores)
- or 3072 cores
- 12288 threads
The system also features the Mont-Blanc optimized software stack, and an InfiniBand EDR interconnect.
Atos announced at ISC 2017 that the blade model developped for the Mont-Blanc prototype would be productized commercialized by Atos as part of its BullSequana X1000 range.
First commercial Arm-based HPC system announced worldwide
Mont-Blanc 1 prototype
8 nodes, each equipped with:
- 2 racks, 8 standard BullX chassis, 72 compute blades fitting 1080 compute cards, for a total of 2160 CPUs and 1080 GPUs.
- SoC Samsung Exynos 5 Dual.
- CPU Cortex-A15@1.7GHz dual core.
- GPU ARM Mali T-604 (OpenCL 1.1 capable).
Documentation to access the Mont-Blanc prototype is available here.
8 nodes, each equipped with:
- Nvidia Tegra K1 SoC
- 4-Plus-1 quad-core ARM Cortex A-15 CPU (4x Cortex-A15 + 1x Cortex-A7)
- Kepler GPU with 192 cores
- 2 Gbyte memory with 64 bit width
- CPU Cortex-A15 Quad @ 2 GHz
- CPU Cortex-A7 Quad @ 1.4 GHz
- CPU Mali-T628 MP6
- Applied Micro APM883208 SoC
- 8 ARM-V8 APM @ 2.4GHz
- 2 DDR3 memory channels with 2x8GB DDR3 UDIMM
- X-C1 Development Kit Plus
70 nodes, each equiped with:
- CPU Cortex-A9 Quad @1.4 GHz
- GPU Nvidia Tesla K20
- 4 GB DDR3 RAM
- 1 Gb Ethernet interconnection network
- QDR Infiniband interconnection*