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Mont-Blanc 2020 demonstrator

The Mont-Blanc 2020 demonstrator is a key output of the project.

The prototype will run on an emulator platform; it will be based on trace-based SVE traffic generators combined with the RTL model of the NoC and the full memory hierarchy. Its objectives:

  •  validation of the design and the associated toolchain in the context of real-life applications,
  • cycle-accurate evaluation of performance at SoC level that will be extrapolated to predict the impact of MB2020 designs for a full HPC system targeting Exascale computing.

The Mentor Veloce emulation platform

Emulation is the process of using a hardware / software based platform that mimics the physical behaviour of an Integrated Circuit / System-on-Chip design. It is an essential process for the development of complex digital circuits. Mont-Blanc 2020 benefits from the Mentor Veloce2 emulator platform installed at its partner CEA.

One thousand times faster than traditional simulation tools, Veloce allows to test, debug and validate SoCs at an early stage of their design, using real-world data.

Mont-Blanc 3 prototype: Dibona

As part of the Phase 3 of Mont-Blanc, Atos built a new Arm-based prototype, which is available to the Mont-Blanc partners and end-users to test our software and scientific applications on a state-of-the-art Arm architecture.

It is named Dibona, after the Dibona peak in the French Alps, and it started operation in Fall 2017. It is based on 64 bit ThunderX2 processors from Marvell®, relying on the Arm® v8 instruction set. The prototype leverages the BullSequana X1000 infrastructure, including ultra efficient Direct Liquid Cooling – cooling with warm water. The full configuration includes:

  • 48 bi-socket computes nodes
  • ie. 96 Marvell® ThunderX2 CPUs (32 cores)
  • or 3072 cores
  • 12288 threads

The system also features the Mont-Blanc optimized software stack, and an InfiniBand EDR interconnect.

Three compute nodes are integrated side by side in each BullSequana blade.

Atos announced at ISC 2017 that the blade model developped for the Mont-Blanc prototype would be productized commercialized by Atos as part of its BullSequana X1000 range.

First commercial Arm-based HPC system announced worldwide

Mont-Blanc 1 prototype

8 nodes, each equipped with:

Documentation to access the Mont-Blanc prototype is available here.


Jetson TK1

8 nodes, each equipped with:

  • Nvidia Tegra K1 SoC
  • 4-Plus-1 quad-core ARM Cortex A-15 CPU (4x Cortex-A15 + 1x Cortex-A7)
  • Kepler GPU with 192 cores
  • 2 Gbyte memory with 64 bit width



  • CPU Cortex-A15 Quad @ 2 GHz
  • CPU Cortex-A7 Quad @ 1.4 GHz
  • CPU Mali-T628 MP6



24 nodes, each node is equiped with:

  • SoC Samsung Exynos 5 Octa 5410
  • CPU Cortex-A15@1.6GHz quad core and Cortex-A7@1.2GHz quad core
  • GPU PowerVR SGX544MP3 – No OpenCL support available
  • 2Gbyte LPDDR3 RAM PoP
  • 1 Gb Ethernet interconnection


70 nodes, each equiped with:

  • CPU Cortex-A9 Quad  @1.4 GHz
  • GPU Nvidia Tesla K20
  • 4 GB DDR3 RAM
  • 1 Gb Ethernet interconnection network
  • QDR Infiniband interconnection*

*IPoverIB only


3 nodes, each node is equipped with: